“decimation filter”造句，怎麼用decimation filter造句

5、According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.

1、Design of FIR decimation filter based on FPGA

3、The on-chip decimation filter is configured for maximum performance and flexibility.

6、The converter USES a high order MASH noise shaping technique and a digital decimation filtering part consisting of comb filters and cascade of half band filters.

4、An on-board digital multiplexer allows the user to access data from the various stages of the decimation filter.

2、Design of decimation filter of ∑-Δ microgravity accelerometers